1. Field of the Invention
The present invention is in the field of process technology for the manufacture of semiconductor solid-state devices or of parts thereof. More specifically, the present invention relates to the manufacture of a semiconductor structure and components using processes to integrate semiconducting components of different crystalline orientation within the same substrate.
2. Description of the Related Art
Semiconductor structures having components with different crystal orientations are of particular interest for the fabrication of high mobility metal-oxide semiconductor field effect transistors (MOSFETs) both in vertical or lateral architecture. The mobility of electrons and holes in silicon MOSFETs depends on the surface orientation of the crystals and are the highest for electrons in <100> and holes in <110> or <111> orientations. It is thus of technological interest to combine both silicon orientations on a single wafer.
This is currently achieved only by wafer bonding of silicon with different crystal orientation. (See U.S. Pat. Nos. 7,023,057, 7,023,055, and 7,041,538). An alternative process relies on a method to selectively grow epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. (See U.S. Pat. No. 6,555,891). The SOI structure includes a buried silicon oxide layer (BOX) on a bulk silicon substrate having, for example, a <100> orientation, covered with a silicon layer of another orientation, e.g. <110>.
Future MOSFETs will rely on higher device density and combinations of novel materials, such as III-V and II-VI semiconductors, and germanium (Ge) which have higher charge carrier mobility than silicon. However, because of physical and/or economical reasons, large Ge or III-V substrates are not currently available. Thus, a process to grow areas of high mobility semiconductors on readily available silicon wafers is of significant interest. So far, however, attempts to grow, for example, III-V materials on silicon are hampered by the lattice mismatch of the semiconducting crystals.
Vapor-Liquid-Solid (VLS) growth is known for selective growth of semiconducting nanowires using a catalytic nano-particle, typically made from gold (Au). See “Semiconductor Nanowires: From Self-Organization to Patterned Growth”, Hong Jin Fan et al., small 2006, 2, No. 6, pages 700-717. It was observed that the crystal orientation of epitaxial and non-epitaxial silicon nanowires (SiNWs) depends on the diameter of the SiNW. SiNWs having diameters larger than 30 nm grow exclusively in the <111> direction. See “Diameter-Dependent Growth Direction of Epitaxial Silicon Nanowires”, V. Schmidt et al., nanoletters 2005, Vol. 5, No. 5, pages 931-935, and “Controlled Growth and Structures of Molecular-Scale Silicon Nanowires” Yue WU et al., Nanoletters, 2004, Vol. 4, No. 3, pages 433-436. Further, VLS-growth of epitaxial III-V and Ge nanowires (NWs) on Si has been reported. VLS growth of epitaxial and random oriented silicon nanowires within the pores of anodized aluminum oxide membranes has been demonstrated. See “Template-directed vapor-liquid-solid growth of silicon nanowires”, Kok-Keong Lew et al., Journal of Vacuum Science and Technology B 20(1), January/February 2002, pages 389-392. Further, VLS growth of epitaxial and random oriented silicon nanowires within porous organosilicate thin films has also been demonstrated. See “Templated germanium nanowire synthesis using oriented mesoporous organosilicate thin films” H. Jagannathan et al., Journal of Vacuum Science and Technology B 24(5), September/October 2006, pages 2220-2224. In these cases the pores act as guides or templates for the VLS growth (templated growth). VLS based methods to grow epitaxial Ge layers on Si has been reported but only on a flat, non structured surface. See “Liquid-metal-mediated homoepitaxial film growth of Ge at low temperature”, F. Xiong et al., Applied Physic Letters 59 (27), 30 Dec. 1991, pages 3586-3588. Finally, doping during VLS-growth of nanowires has also been demonstrated.
It would be of benefit in the field to have a more ideal semiconductor structure for high mobility device fabrication and a manufacturing process for such semiconductor structure.